Minimizing Interacting Finite State Machines
Memorandum No. UCB/ERL M93/68, 9 September 1993
29 Pages Posted: 17 Nov 2020
Date Written: 1993
We address the problem of minimizing collections of interacting finite state machines that arise in the context of formal verification. Typically much of the behavior of the system is redundant with respect to a given property being verified, and so the system can be replaced by substantially simpler representations. These redundancies can be captured by a series of equivalence relations on the state space. Directly minimizing the system requires forming the complete product machine which can be very large. We describe hierarchical procedures that minimize the system with respect to explicit and implicit representations. We present experimental results on some standard verification examples to show that our algorithms allow the product machine to be represented by very small implicit or explicit representations. We conclude with some further directions.
Keywords: very large scale integrated circuits, computer aided design, formal verification, logic synthesis
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